In charge-domain signal-processing circuits, signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by periodic clock voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability. This capability is well-suited to performing analog-to-digital conversion using pipeline algorithms. Charge-domain circuits are implemented as charge-coupled devices (CCDs), as MOS bucket-brigade devices (BBDs), and as bipolar BBDs. The present invention pertains to MOS and bipolar BBDs.
Charge-redistribution analog-to-digital converters (ADCs) implement a successive-approximation A/D conversion algorithm by iterated comparison and conditional capacitor switching in a single stage. They are capable of providing very high precision and resolution (up to 18 bits in currently-known implementations) at relatively low sample rates, with low power consumption.
Pipelined analog-to-digital converters (ADCs) are commonly used in applications requiring high sample rates and high resolution. Pipelined ADCs implement the successive-approximation algorithm by resolving one or several bits at each pipeline stage, subtracting the quantized estimate from the signal at that stage, and propagating the residue to the next pipeline stage for further processing. Pipelined ADCs have been implemented using a variety of circuit techniques, including switched-capacitor circuits and charge-domain circuits. The present invention pertains to charge-domain pipelined ADCs.